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The purpose of this paper is to propose a time‐dependent mobility degradation model which is independent from the process or operating conditions.

In total, four transistors under test are electrically stressed using constant positive electrical stress voltage technique with the gate bias of V_G=40 V DC, where the source and drain were grounded. The authors increased the stress voltage step by step to avoid electrostatic discharge and recorded the I_D‐V_DS and I_D‐V_GS measurements in time intervals during the stress.

The experimental results show that the output current and the threshold voltage of the transistor are increased after the stress. Mobility and channel length are decreased. The changes in the transistor parameters were associated to interface state Si/SiO₂ effects. The authors used the physical changes in transistor and proposed a new‐time dependent mobility degradation model. The mobility change was calculated using the proposed model and compared with the experimental results. It was seen that the calculated and experimental results are in good agreement.

This is an original research paper and enables the mobility degradation to be predicted independently from effects of process or operational changes such as oxide thickness, substrate doping, and applied voltages on transistor.